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1 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5715/4 ? idt72v70840 3.3 volt time slot interchange digital switch 4,096 x 4,096 idt and the idt logo are registered trademarks of integrated device technology, inc. the st-bus ? is a trademark of mitel corp.

? ? ? ? ? 32 serial input and output streams ? ? ? ? ? 4,096 x 4,096 channel non-blocking switching at 8.192 mb/s ? ? ? ? ? accepts data streams at 2.048 mb/s, 4.096 mb/s or 8.192 mb/s ? ? ? ? ? per-channel variable delay mode for low-latency applications ? ? ? ? ? per-channel constant delay mode for frame integrity applica- tions ? ? ? ? ? automatic identification of st-bus ? and gci serial streams ? ? ? ? ? automatic frame offset delay measurement ? ? ? ? ? per-stream frame delay offset programming ? ? ? ? ? per-channel high impedance output control ? ? ? ? ? per-channel processor mode to allow microprocessor writes to tx streams ? ? ? ? ? direct microprocessor access to all internal memories ? ? ? ? ? memory block programming for quick set-up ? ? ? ? ? ieee-1149.1 (jtag) test port ? ? ? ? ? internal loopback for testing ? ? ? ? ? available in 144-pin thin quad flatpack (tqfp) and 144-pin ball grid array (bga) packages ? ? ? ? ? operating temperature range -40 c to +85 c ? ? ? ? ? 3.3v i/o with 5v tolerant inputs and ttl compatible outputs the idt72v70840 has a non-blocking switch capacity of 1,024 x 1,024 channels at 2.048 mb/s, 2,048 x 2,048 channels at 4.096 mb/s, and 4,096 x 4,096 channels at 8.192 mb/s. with 32 inputs and 32 outputs, programmable per stream control, and a variety of operating modes the idt72v70840 is designed for the tdm time slot interchange function in either voice or data applications. some of the main features of the idt72v70840 are low power 3.3 volt operation, automatic st-bus ? /gci sensing, memory block programming, simple microprocessor interface, one cycle direct internal memory accesses, output mux receive serial data streams rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 ode f0i vcc cs ds r/ w a0-a13 gnd dta d0-d15 5715 drw01 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 loopback test port data memory internal registers microprocessor interface timing unit tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 tx8 tx9 tx10 tx11 tx12 tx13 tx14 tx15 clk fe/ hclk wfps tdi tms tck tdo trst reset rx16 rx17 rx18 rx19 rx20 rx21 rx22 rx23 rx24 rx25 rx26 rx27 rx28 rx29 rx30 rx31 tx16 tx17 tx18 tx19 tx20 tx21 tx22 tx23 tx24 tx25 tx26 tx27 tx28 tx29 tx30 tx31 connection memory transmit serial data streams
2 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 tx11 tx10 gnd tx9 tx8 v cc rx15 rx14 rx13 rx12 rx11 rx10 rx9 rx8 gnd tx7 tx6 tx5 tx4 gnd tx3 tx2 tx1 tx0 gnd rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 rx31 rx30 rx29 rx28 rx27 rx26 rx25 rx24 gnd tx23 tx22 tx21 tx20 gnd tx19 tx18 tx17 tx16 gnd rx23 rx22 rx21 rx20 rx19 rx18 rx17 rx16 tx15 tx14 gnd tx13 tx12 v cc tx24 tx25 gnd tx26 tx27 tx28 tx29 gnd tx30 tx31 d0 d1 gnd d2 d3 d4 d5 gnd d6 d7 v cc d08 d09 gnd d10 d11 v cc d12 d13 gnd d14 d15 gnd a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a0 r/ gnd
tck tdo tdi tms v cc wfps fe/hclk clk gnd
ode gnd a1 5715 drw 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc tqfp: 0.50mm pitch, 20mm x 20mm (da144, order code: da; dag 144, order code: dag) top view note: 1. all i/o pins are 5v tolerant except for tms, tdi and trst vsewscvf0ravs
3 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 symbol name i/o description gnd ground. ground rail. v cc v cc +3.3 volt power supply. tx0-31 tx output 0 to 31 o serial data output stream. these streams may have a data rate of 2.048 mb/s, 4.096 mb/s or 8.192 mb/s. (three-state outputs) rx0-31 rx input 0 to 31 i serial data input stream. these streams may have a data rate of 2.048 mb/s, 4.096 mb/s or 8.192 mb/s. frame pulse i this input accepts and automatically identifies frame synchronization signals formatted according to st-bus ? and gci specifications. fe/hclk frame evaluation/ i when low, this pin is the frame measurement input. when high, the hclk (4.096 mhz clock) is required hclk clock if this pin is unused, an external pull-up or pull-down must be provided. clk clock i serial clock for shifting data in/out on the serial streams (rx/tx 0-31). this input accepts a 4.096 mhz clock when data streams @ 2.048 mb/s, a 8.192 mhz clock when data streams @ 4.096 mb/s, a 16.384 mhz clock when data streams @ 8.192 mb/s. tms test mode select i jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an intern al pull-up when not driven. tdi test serial data in i jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up when not driven. tdo test serial data out o jtag serial data is output on this pin on the falling edge of tck. this pin is held in high-impedance s tate when jtag scan is not enabled. tck test clock i provides the clock to the jtag test logic. test reset i asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin is pulled by an internal pull-up when not driven. this pin should be pulsed low on power-up, or held low, to ensure that the idt72v70840 is in the normal functional mode. device reset i this input (active low) puts the idt72v70840 in its reset state that clears the device internal counters, (schmitt trigger input) registers and brings tx0-31 and microport data outputs to a high-impedance state. the time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. in normal operation, the pin must be held low for a minimum of 100ns to reset the device. wfps wide frame pulse select i when 1, enables the wide frame pulse (sfp) frame alignment interface. when 0, the device operates in st-bus ? /gci mode. data strobe i this active low input works in conjunction with
to enable the read and write operations. r/ read/write i this input controls the direction of the data bus lines during a microprocessor access.
chip select i active low input used by a microprocessor to activate the microprocessor port of idt72v70840. a0-13 address bus 0 to 13 i these pins allow direct access to connection memory, data memory and internal control registers. d0-15 data bus 0-15 i/o these pins are the data bits of the microprocessor port. data transfer o this active low signal indicates that a data bus transfer is complete. when the bus cycle ends, this pin acknowledgment drives high and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. a pull-up resistor is required to hold a high level when the pin is in high-impedance. ode output drive enable i this is the output enable control for the tx0-31 serial outputs. when ode input is low and the osb bit o f the cr register is low, tx0-31 are in a high-impedance state. if this input is high, the tx0-31 output drivers are enabled. however, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory. for frame alignment in the wide frame pulse (wfp) mode. there is no internal pull-up or pull-down.
4 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 jtag test access port (tap) and per stream programmable input offset delay, variable or constant throughput modes, internal loopback, output enable, and processor mode. the idt72v70840 is capable of switching up to 4,096 x 4,096 channels without blocking. designed to switch 64 kbit/s pcm or n x 64 kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per channel basis. the 32 serial input streams (rx) of the idt72v70840 can be run up to 8.192 mb/s allowing 128 channels per 125 s frame. the data rates on the output streams (tx) are identical to those on the input stream. with two main operating modes, processor mode and connection mode, the idt72v70840 can easily switch data from incoming serial streams (data memory) or from the controlling microprocessor (connection memory). as control and status information is critical in data transmission, the processor mode is especially useful when there are multiple devices sharing the input and output streams. with data coming from multiple sources and through different paths, data entering the device is often delayed. to handle this problem, the idt72v70840 has a frame evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +4.5 clock cycles. the idt72v70840 also provides a jtag test access port, an internal loopback feature, memory block programming, a simple microprocessor interface and automatic st-bus ? /gci sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities.
data and connection memory all data that comes in through the rx inputs go through a serial-to-parallel conversion before being stored into internal data memory. the 8 khz frame pulse ( ) is used to mark the 125 s frame boundaries and to sequentially address the input channels in data memory. data output on the tx streams may come from either the serial input streams (data memory) or from the microprocessor (connection memory). in the case that rx input data is to be output, the addresses in connection memory are used to specify a stream and channel of the input. the connection memory is setup in such a way that each location corresponds to an output channel for each particular stream. in that way, more than one channel can output the same data. in processor mode, the microprocessor writes data to the connection memory locations corresponding to the stream and channel that is to be output. the lower half (8 least significant bits) of the connection memory is output every frame until the microprocessor changes the data or mode of the channel. by using this processor mode capability, the microprocessor can access input and output time-slots on a per channel basis. the four most significant bits of the connection memory are used to control per channel functions of the out put streams. specifically, there are bits for processor or connection mode, constant or variable delay, enables or disables of output drivers, and controls for the loopback function. if the per channel oe is set to zero, only that particular channel (8-bits) will be in the high-impedance state. if however, the ode input pin is low or the output standby bit (osb) in the control register is low, all of the outputs will be in a high-impedance state even if a particular channel in connection memory has enabled the output for that channel. in other words, the ode pin and osb control bit are master output enables for the device (table 3). serial data interface timing the master clock frequency must always be twice the data rate, e.g. for a serial data rates of 2.048 mb/s, the master clock (clk) must be at 4.096 mhz. the input and output stream data rates will always be identical. see control register bits dr1-0 description (table 5) for data and clock rate selections. the idt72v70840 provides two different interface timing modes, st-bus ? or gci. the idt72v70840 automatically detects the presence of an input frame pulse and identifies it as either st-bus ? or gci. in st-bus ? format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of clk, three quarters of the way into the bit cell. in gci format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of clk at three quarters of the way into the bit cell. input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. ). although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. because data is often delayed this feature is useful in compensating for the skew between clocks. each input stream can have its own delay offset value by programming the frame input offset registers (for, table 8). the maximum allowable skew is +4 master clock (clk) periods forward with a resolution of 1/2 clock period. the output frame offset cannot be offset or adjusted. serial input frame alignment evaluation the idt72v70840 provides the frame evaluation (fe) input to determine different data input delays with respect to the frame pulse . a measurement cycle is started by setting the start frame evaluation (sfe) bit low for at least one frame. when the sfe bit in the control register is changed from low to high, the evaluation starts. two frames later, the complete frame evaluation (cfe) bit of the frame alignment register (far) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the far register. the sfe bit must be set to zero before a new measurement cycle is started. in st-bus ? mode, the falling edge of the frame measurement signal (fe) is evaluated against the falling edge of the st-bus ? frame pulse. in gci mode, the rising edge of fe is evaluated against the rising edge of the gci frame pulse. see table 7 and figure 1 for the description of the frame alignment register. memory block programming the idt72v70840 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 12 to 15 of every connection memory location, first program the desired pattern in bits 5 to 8 of the control register. the block programming mode is enabled by setting the memory block program (mbp) bit of the control register high. when the block programming enable (bpe) bit of the control register is set to high, the block programming data will be loaded into the bits 12 to 15 of every connection memory location. the other connection memory bits (bit 0 to bit 11) are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero.
5 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 loopback control the loopback control (lpbk) bit of each connection memory location allows the tx output data to be looped backed internally to the rx input for diagnostic purposes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., data from txn channel m routes to the rxn channel m internally); if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabili- ties on a per-channel basis. for voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the /c bit of the connection memory. variable delay mode ( v v
6 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 ! a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w location 1 1 sta4 sta3 sta2 sta1 sta0 ch6 ch5 ch4 ch3 ch2 ch1 ch0 r data memory 1 0 sta4 sta3 sta2 sta1 sta0 ch6 ch5 ch4 ch3 ch2 ch1 ch0 r/w connect. memory 0 1 0 0 0 0 x x x x x x x x r/w control register 0 1 0 0 0 1 x x x x x x x x r/w frame align register 0 1 0 0 1 0 x x x x x x x x r/w for0 0 1 0 0 1 1 x x x x x x x x r/w for1 0 1 0 1 0 0 x x x x x x x x r/w for2 0 1 0 1 0 1 x x x x x x x x r/w for3 0 1 0 1 1 0 x x x x x x x x r/w for4 0 1 0 1 1 1 x x x x x x x x r/w for5 0 1 1 0 0 0 x x x x x x x x r/w for6 0 1 1 0 0 1 x x x x x x x x r/w for7 oe bit in connection ode pin osb bit in cr tx stream output memory register status 0 don?t care don?t care per channel high-impedance 1 0 0 high-impedance 1 0 1 enable 1 1 0 enable 1 1 1 enable "! #! delay for constant throughput delay mode input rate (m ? output channel number) (n ? input channel number) 2.048 mb/s 32 + (32 ? n) +m time-slots 4.096 mb/s 64 + (64 ? n) +m time-slots 8.192 mb/s 128 + (128 ? n) +m time-slots ! delay for variable throughput delay mode input rate (m ? output channel number; n ? input channel number) m < n m = n, n+1, n+2 m > n+2 2.048 mb/s 32 ? (n-m) time-slots (m-n + 32) time-slots (m-n) time-slots 4.096 mb/s 64 ? (n-m) time-slots (m-n + 64) time-slots (m-n) time-slots 8.192 mb/s 128 ? (n-m) time-slots (m-n + 128) time-slots (m-n) time-slots
7 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 reset value: 0000 h . bit name description 15-10 unused must be zero for normal operation. 9 mbp when 1, the connection memory block programming feature is ready for the programming of connection memory high bits, (memory block program) bit 11 to bit 15. when 0, this feature is disabled. 8-5 bpd3-0 these bits carry the value to be loaded into the connection memory block whenever the memory block programming feature (block programming data) is activated. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the co ntents of the bits bpd3-0 are loaded into bit 15 and 12 of the connection memory. bit 11 to bit 0 of the connection memory are set to 0. 4 bpe a zero to one transition of this bit enables the memory block programming function. the bpe and bpd4-0 bits in the cr (begin block register have to be defined in the same write operation. once the bpe bit is set high, the device requires two fram es to programming enable) complete the block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is completed. when the bpe = 1, the bpe or mbp can be set to 0 to abort to ensure proper operation. when bpe = 1, the other bit in the cr register must not be changed for two frames to ensure proper operation. 3 osb when ode = 0 and osb = 0, the output drivers of tx0 to tx31 are in high impedance mode. when ode = 0 and osb = 1, (output stand by) the output driver of tx0 to tx31 function normally. when ode = 1, tx0 to tx31 output drivers function normal ly. 2 sfe a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far register changes f rom (start frame evaluation) zero to one, the evaluation procedure stops. to start another fame evaluation cycle, set this bit to z ero for at least one frame. 1-0 dr1-0 dr1 dr0 data rate master clock (data rate select) 0 0 2.048 mb/s 4.096 mhz 0 1 4.096 mb/s 8.192 mhz 1 0 8.192 mb/s 16.384 mhz 1 1 reserved reserved 1514131211109876543210 000000mbp bpd3 bpd2 bpd1 bpd0 bpe osb sfe dr1 dr0 $! %! bit name description 15 lpbk when 1, the rx n channel m data comes from the tx n channel m. for proper per channel loopback operations, set the delay (per channel loopback) offset register bits ofn[2:0] to zero for the streams which are in the loopback mode. 14 /c (variable/constant this bit is used to select between the variable (low) and constant delay (high) mode on a per-channel basi s. throughput delay) 13 p c when 1, the contents of the connection memory are output on the corresponding output channel and stream. only the lower (processor channel) byte (bit 7 ? bit 0) will be output to the tx output pins. when 0, the contents of the connection memory are the data memory address of the switched input channel and stream. 12 oe this bit enables the tx output drivers on a per-channel basis. when 1, the output driver functions normally. when 0, the ou tput (output enable) driver is in a high-impedance state. 11-7 sab4-0 (source stream the binary value is the number of the data stream for the source of the connection. address bits) 6-0 cab6-0 (source channel the binary value is the number of the channel for the source of the connection. address bits) 1514131211109876543210 lpbk v
8 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 0123 456 78 9101112131415 16 st-bus frame clk offset value fe input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gci frame clk offset value fe input (fd[10:0] = 06 h ) (fd11 = 0, sample at clk low phase) (fd[10:0] = 09 h ) (fd11 = 1, sample at clk high phase) 5715 drw 04 figure 1. example for frame alignment measurement bit name description 15-13 unused must be zero for normal operation 12 cfe (complete when cfe = 1, the frame evaluation is completed and bits fd10 to fd0 bits contains a valid frame alignment offse t. this bit is reset to frame evaluation) zero, when sfe bit in the cr register is changed from 1 to 0. 11 fd11 the falling edge of fe (or rising edge for gci mode) is sampled during the clk-high phase (fd11 = 1) or during the clk-low phas e (frame delay bit 11) (fd11 = 0). this bit allows the measurement resolution to ? clk cycle. 10-0 fd10-0 the binary value expressed in these bits refers to the measured input offset value. these bits are rest to zero when the sfe bi t of the (frame delay bits) cr register changes from 1 to 0. (fd10 ? msb, fd0 ? lsb) reset value: 0000 h . 1514131211109876543210 0 0 0 cfe fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 !

9 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 !

reset value: 0000 h for all for registers. 1514131211109876543210 of32 of31 of30 dle3 of22 of21 of20 dle2 of12 of11 of10 dle1 of02 of01 of00 dle0 for0 register 1514131211109876543210 of72 of71 of70 dle7 of62 of61 of60 dle6 of52 of51 of50 dle5 of42 of41 of40 dle4 for1 register 1514131211109876543210 of112 of111 of110 dle11 of102 of101 of100 dle10 of92 of91 of90 dle9 of82 of81 of80 dle8 for2 register 1514131211109876543210 of312 of311 of310 dle31 of142 of141 of140 dle14 of132 of131 of130 dle13 of122 of121 of120 dle12 for3 register 1514131211109876543210 of192 of191 of190 dle19 of182 of181 of180 dle18 of172 of171 of170 dle17 od162 od161 of160 dle16 for4 register 1514131211109876543210 of232 of231 of230 dle23 of222 of221 of220 dle22 of212 of211 of210 dle21 of202 of201 of200 dle20 for5 register 1514131211109876543210 of272 of271 of270 dle27 of262 of261 of260 dle26 of252 of251 of250 dle25 of242 of241 of240 dle24 for6 register 1514131211109876543210 of312 of311 of310 dle31 of302 of301 of300 dle30 of292 of291 of290 dle29 of282 of281 of280 dle28 for7 register name (1) description ofn2, ofn1, ofn0 these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the rx i nput pin: i.e., to start a new frame. (offset bits 2, 1 & 0) the input frame offset can be selected to +4.5 clock periods from the point where the external frame puls e input signal is applied to the input of the device. see figure 1. dlen st-bus ? mode: dlen = 0, if clock rising edge is at the ? point of the bit cell. (data latch edge) dlen = 1, if when clock falling edge is at the ? of the bit cell. gci mode: dlen = 0, if clock falling edge is at the ? point of the bit cell. dlen = 1, if when clock rising edge is at the ? of the bit cell. note: 1. n denotes an input stream number from 0 to 31.
10 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 st-bus f0i f0i fd11 fd2 fd1 fd0 ofn2 ofn1 ofn0 dlen no clock period shift (default) 10000000 + 0.5 clock period shift 00000001 + 1.0 clock period shift 10010010 + 1.5 clock period shift 00010011 + 2.0 clock period shift 10100100 + 2.5 clock period shift 00100101 + 3.0 clock period shift 10110110 + 3.5 clock period shift 00110111 + 4.0 clock period shift 11001000 + 4.5 clock period shift 01001001 &!

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* figure 2. examples for input offset delay timing
11 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 the idt72v70840 jtag interface conforms to the boundary-scan stan- dard ieee-1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. test access port (tap) the test access port (tap) provides access to the test functions of the idt72v70840. it consists of three input pins and one output pin. test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remain independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to v cc when it is not driven from an external source. test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v cc when it is not driven from an external source. test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. test reset ( ) reset the jtag scan structure. this pin is internally pulled to v cc . instruction register in accordance with the ieee-1149.1 standard, the idt72v70840 uses public instructions. the idt72v70840 jtag interface contains a two-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. see table below for instruction decoding. value instruction function 11 bypass select bypass register 10 sample/preload select boundary scan register 01 sample/preload select boundary scan register 00 extest select boundary scan register test data register as specified in ieee-1149.1, the idt72v70840 jtag interface contains two test data registers: the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the idt72v70840 core logic. the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. the idt72v70840 boundary scan register bits are shown in table 10. bit 0 is the first bit clocked out. all three-state enable bits are active high. jtag instruction register decoding
12 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 # ! boundary scan bit 0 to bit 167 device pin three-state output input control scan cell scan cell rx27 92 rx26 93 rx25 94 rx24 95 tx23 96 97 tx22 98 99 tx21 100 101 tx20 102 103 tx19 104 105 tx18 106 107 tx17 108 109 tx16 110 111 rx23 112 rx22 113 rx21 114 rx20 115 rx19 116 rx18 117 rx17 118 rx16 119 tx15 120 121 tx14 122 123 tx13 124 125 tx12 126 127 tx11 128 129 tx10 130 131 tx9 132 133 tx8 134 135 rx15 136 rx14 137 rx13 138 rx12 139 rx11 140 rx10 141 rx9 142 rx8 143 tx7 144 145 tx6 146 147 tx5 148 149 tx4 150 151 tx3 152 153 tx2 154 155 tx1 156 157 tx0 158 159 rx7 160 rx6 161 rx5 162 rx4 163 rx3 164 rx2 165 rx1 166 rx0 167 boundary scan bit 0 to bit 167 device pin three-state output input control scan cell scan cell ode 0 1 clk 2 3 fe/hclk 4 wfps 5 6
7 r/ 8 a0 9 a1 10 a2 11 a3 12 a4 13 a5 14 a6 15 a7 16 a8 17 a9 18 a10 19 a11 20 a12 21 a13 22 23 d15 24 25 26 d14 27 28 29 d13 30 31 32 d12 33 34 35 d11 36 37 38 d10 39 40 41 d9 42 43 44 d8 45 46 47 d7 48 49 50 d6 51 52 53 d5 54 55 56 d4 57 58 59 d3 60 61 62 d2 63 64 65 d1 66 67 68 d0 69 70 71 tx31 72 73 tx30 74 75 tx29 76 77 tx28 78 79 tx27 80 81 tx26 82 83 tx25 84 85 tx24 86 87 rx31 88 rx30 89 rx29 90 rx28 91
13 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 device 1 idt72v70840 device 2 idt72v70840 device 3 idt72v70840 device 4 idt72v70840 rx0-31 rx32-63 tx0-31 tx32-63 5715 drw06 figure 3. creating larger switch matrices creating large switch matrices to create a switch matrix with twice the capacity of a given tsis device, four devices must be used. in the example below, four idt72v70840, 4096 x 4096 channel capacity devices are used to create an 8192 x 8192 channel switch matrix. as can be seen, device #1 and device #2 will receive the same incoming rx0-31 data and thus have the same contents in data memory. on the output side, however device #1 is used to switch data out on to tx0-31 where as device #2 is used to switch out on tx32-63. like wise device #3 and device #4 are used in the same way as device #1 and device #2 but switch rx32-63, to tx0-31 and tx32-63. with this configuration all possible combinations of input and output streams are possible. in short, device #1 is used to switch rx0-31 to tx0-31, device #2 to switch rx0-31 to tx32-63, device #3 to switch rx32- 63 to tx0-31, and device #4 to switch rx32-63 to tx32-63.
14 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 symbol parameter min. typ. max. units i cc (2) supply current @ 2.048 mb/s - 15 20 ma @ 4.096 mb/s - 25 35 ma @ 8.192 mb/s - 47 70 ma i il (3,4) input leakage (input pins) - - 50 ????? ???????????? ????? figure 4. output load symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v vi voltage on digital inputs gnd -0.3 5.3 v i o current at digital outputs -50 50 ma t s storage temperature -55 +125 c p d package power dissapation ? ?????? ???? ?? ? ??
15 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 *
symbol parameter min. typ. max. units t fpw (1) frame pulse width (st-bus ? , gci) bit rate = 2.048 mb/s 26 295 ns bit rate = 4.096 mb/s 26 145 ns bit rate = 8.192 mb/s 26 80 ns t fps (1) frame pulse setup time before clk falling (st-bus ? or gci) 5 ns t fph (1) frame pulse hold time from clk falling (st-bus ? or gci) 10 ns t cp (1) clk period bit rate = 2.048 mb/s 190 300 ns bit rate = 4.096 mb/s 110 150 ns bit rate = 8.192 mb/s 58 70 ns t ch (1) clk pulse width high bit rate = 2.048 mb/s 85 150 ns bit rate = 4.096 mb/s 50 75 ns bit rate = 8.192 mb/s 20 40 ns t cl (1) clk pulse width low bit rate = 2.048 mb/s 85 150 ns bit rate = 4.096 mb/s 50 75 ns bit rate = 8.192 mb/s 20 40 ns t r , t f clock rise/fall time 10 ns t hfpw (2) wide frame pulse width bit rate = 8.192 mb/s 195 295 ns t hfps (2) frame pulse setup time before hclk falling 5 150 ns t hfph (2) frame pulse hold time from hclk falling 10 150 ns t hcp (2) hclk (4.096 mhz) period bit rate = 8.192 mb/s 190 300 ns t hch (2) hclk (4.096 mhz) pulse width high bit rate = 8.192 mb/s 85 150 ns t hcl (2) hclk (4.096 mhz) pulse width low bit rate = 8.192 mb/s 85 150 ns t hr , t hf hclk rise/fall time 10 ns t dif (3) delay between falling edge of hclk and falling edge of clk -10 10 ns notes: 1. wfps pin = 0. 2. wfps pin = 1 3. wfps pin = 0 or 1.
16 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 figure 5. st-bus ? timing symbol parameter min. typ. max. units t sis rx setup time 5 ns t sih rx hold time 10 ns t sod tx delay ? active to active @ 2.048 mb/s 30 ns @ 4.096 mb/s 30 ns @ 8.192 mb/s 30 ns t dz tx delay ? active to high-z @ 2.048 mb/s 30 ns @ 4.096 mb/s 30 ns @ 8.192 mb/s 30 ns t zd tx delay ? high-z to active @ 2.048 mb/s 30 ns @ 4.096 mb/s 30 ns @ 8.192 mb/s 30 ns t ode output driver enable (ode) delay @ 2.048 mb/s 30 ns @ 4.096 mb/s 30 ns @ 8.192 mb/s 30 ns # * , -'. note: 1. high impedance is measured by pulling to the appropriate rail with r l (1k), with timing corrected to cancel time taken to discharge c l (150 pf). note : 1. @ 2.048 mb/s mode, last channel = ch 31, @ 4.096 mb/s mode, last channel = ch 63, @ 8.192 mb/s mode, last channel = ch 127. t fpw t fph t fps clk tx rx t cp 5715 drw08 bit 6, channel 0 bit 7, channel 0 bit 0, last ch (1) bit 5, channel 0 bit 6, channel 0 bit 7, channel 0 bit 5, channel 0 t ch t cl t r t f t sis t sih t sod bit 0, last ch (1)
17 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 figure 8. serial output and external control figure 9. output driver enable (ode) t dz clk (st-bus mode) tx tx valid data hiz valid data hiz t zd clk (gci mode) 5715 drw 10 ode tx valid data hiz hiz 5715 drw12 t ode t ode figure 6. gci timing figure 7. wfp bus timing (@ 8.192 mb/s, when pin wfps is high) clk tx rx 5715 drw09 bit 1, channel 0 bit 0, channel 0 bit 2, channel 0 bit 1, channel 0 bit 0, channel 0 bit 2, channel 0 bit 7, last ch (1) bit 7, last ch (1) t fph t fps t cp t ch t cl t r t f t sis t sih t fpw t sod t hfph t dif tx rx 5715 drw10 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 t hfps t hfpw clk 16.384 mhz hclk 4.096 mhz t hch t hcp t cp t ch t cl t r t sod t f t sis t sih t hcl t hf t hr note : 1. @ 2.048 mb/s mode, last channel = ch 31, @ 4.096 mb/s mode, last channel = ch 63, @ 8.192 mb/s mode, last channel = ch 127.
18 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 *
notes : 1. c l = 150pf 2. r l = 1k 3. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 4. to achieve one clock cycle fast memory access, this setup time, t dss should be met. otherwise, worst case memory access operation is determined by t akd . symbol parameter min. typ. max. units t css cs setup from ds falling 0 ns t rws r/w setup from ds falling 3 ns t ads address setup from ds falling 2 ns t csh cs hold after ds rising 0 ns t rwh r/w hold after ds rising 3 ns t adh address hold after ds rising 2 ns t ddr (1) data setup from dta low on read 2 ns t dhr (1,2,3) data hold on read 10 15 25 ns t dsw data setup on write (fast write) 10 ns t swd valid data delay on write (slow write) - 0ns t dhw data hold on write 5 ns t akd (1) acknowledgment delay: reading/writing registers 30 ns reading/writing memory @ 2.048 mb/s 345 ns @ 4.096 mb/s 200 ns @ 8.192 mb/s 120 ns t akh (1,2,3) acknowledgment hold time 20 ns t dss (4) data strobe setup time 2 ns
19 commercial temperature range idt72v70840 3.3v time slot interchange digital switch 4,096 x 4,096 ds 5715 drw13 valid write data d0-d15 read valid read data valid address t akh d0-d15 write r/ a0-a11 clk gci clk st-bus ?
20 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com
5715 drw14 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 72v70840 4,096 x 4,096 3.3v time slot interchange digital switch da dag thin quad flatpacks (tqfp, da144) green thin quad flatpacks (tqfp, dag144) 5/05/2000 pg. 1 6/08/2000 pgs. 1, 2, 3 and 19. 8/30/2000 pgs. 2, 4, 6, 9, 11, 13, 14, 16, 17 and 19. 01/24/2001 pg. 14 10/22/2001 pg. 1. 1/04/2002 pgs. 1 and 15.
12 /14/2006 pgs. 2 and 20. 10/06/2008 pg. 3.

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